The invention pertains to non-volatile devices, and in particular aspects pertains to semiconductor-on-insulator (SOI) constructions comprising non-volatile memory and/or non-volatile logic devices. The devices can utilize thin film transistors (TFTs). Exemplary non-volatile memory and logic devices are programmable erasable read-only memory (PROM/EPROM) devices, electronically-erasable programmable read-only memory (EEPROM) devices, field programmable gate arrays (FPGA), and flash memory devices. In some aspects the invention pertains to electronic systems comprising non-volatile memory and/or logic devices.
SOI technology differs from traditional bulk semiconductor technologies in that the active semiconductor material of SOI technologies is typically much thinner than that utilized in bulk technologies. The active semiconductor material of SOI technologies will typically be formed as a thin film over an insulating material (typically oxide), with exemplary thicknesses of the semiconductor film being less than or equal to 2000 xc3x85. In contrast, bulk semiconductor material will typically have a thickness of at least about 200 microns. The thin semiconductor of SOI technology can allow higher performance and lower power consumption to be achieved in integrated circuits than can be achieved with similar circuits utilizing bulk materials.
An exemplary integrated circuit device that can be formed utilizing SOI technologies is a so-called thin film transistor (TFT), with the term xe2x80x9cthin filmxe2x80x9d referring to the thin semiconductor film of the SOI construction. In particular aspects, the semiconductor material of the SOI construction can be silicon, and in such aspects the TFTs can be fabricated using recrystallized amorphous silicon or polycrystalline silicon. The silicon can be supported by an electrically insulative material (such as silicon dioxide), which in turn is supported by an appropriate substrate. Exemplary substrate materials include glass, bulk silicon and metal-oxides (such as, for example, Al2O3). If the semiconductor material comprises silicon, the term SOI is occasionally utilized to refer to a silicon-on-insulator construction, rather than the more general concept of a semiconductor-on-insulator construction. However, it is to be understood that in the context of this disclosure the term SOI refers to semiconductor-on-insulator constructions. Accordingly, the semiconductor material of an SOI construction referred to in the context of this disclosure can comprise other semiconductive materials in addition to, or alternatively to, silicon; including, for example, germanium.
A problem associated with conventional TFT constructions is that grain boundaries and defects can limit carrier mobilities. Accordingly, carrier mobilities are frequently nearly an order of magnitude lower than they would be in bulk semiconductor devices. High voltage (and therefore high power consumption), and large areas are utilized for the TFTs, and the TFTs exhibit limited performance. TFTs thus have limited commercial application and currently are utilized primarily for large area electronics.
Various efforts have been made to improve carrier mobility of TFTs. Some improvement is obtained for devices in which silicon is the semiconductor material by utilizing a thermal anneal for grain growth following silicon ion implantation and hydrogen passivation of grain boundaries (see, for example, Yamauchi, N. et al., xe2x80x9cDrastically Improved Performance in Poly-Si TFTs with Channel Dimensions Comparable to Grain Sizexe2x80x9d, IEDM Tech. Digest, 1989, pp. 353-356). Improvements have also been made in devices in which a combination of silicon and germanium is the semiconductor material by optimizing the germanium and hydrogen content of silicon/germanium films (see, for example, King, T. J. et al, xe2x80x9cA Low-Temperature ( less than =550xc2x0 C.) Silicon-Germanium MOS TFT Technology for Large-Area Electronicsxe2x80x9d, IEDM Tech. Digest, 1991, pp. 567-570).
Investigations have shown that nucleation, direction of solidification, and grain growth of silicon crystals can be controlled selectively and preferentially by excimer laser annealing, as well as by lateral scanning continuous wave laser irradiation/anneal for recrystallization (see, for example, Kuriyama, H. et al., xe2x80x9cHigh Mobility Poly-Si TFT by a New Excimer Laser Annealing Method for Large Area Electronicsxe2x80x9d, IEDM Tech. Digest, 1991, pp. 563-566; Jeon, J. H. et al., xe2x80x9cA New Poly-Si TFT with Selectively Doped Channel Fabricated by Novel Excimer Laser Annealingxe2x80x9d, IEDM Tech. Digest, 2000, pp. 213-216; Kim, C. H. et al., xe2x80x9cA New High-Performance Poly-Si TFT by Simple Excimer Laser Annealing on Selectively Floating a Si Layerxe2x80x9d, IEDM Tech. Digest, 2001, pp. 753-756; Hara, A. et al, xe2x80x9cSelective Single-Crystalline-Silicon Growth at the Pre-Defined Active Regions of TFTs on a Glass by a Scanning CW Layer Irradiationxe2x80x9d, IEDM Tech. Digest, 2000, pp. 209-212; and Hara, A. et al., xe2x80x9cHigh Performance Poly-Si TFTs on a Glass by a Stable Scanning CW Laser Lateral Crystallizationxe2x80x9d, IEDM Tech. Digest, 2001, pp. 747-750). Such techniques have allowed relatively defect-free large crystals to be grown, with resulting TFTs shown to exhibit carrier mobility over 300 cm2/V-second.
Another technique which has shown promise for improving carrier mobility is metal-induced lateral recrystallization (MILC), which can be utilized in conjunction with an appropriate high temperature anneal (see, for example, Jagar, S. et al., xe2x80x9cSingle Grain TFT with SOI CMOS Performance Formed by Metal-Induced-Lateral-Crystallizationxe2x80x9d, IEDM Tech. Digest, 1999, p. 293-296; and Gu, J. et al., xe2x80x9cHigh Performance Sub-100 nm Si TFT by Pattern-Controlled Crystallization of Thin Channel Layer and High Temperature Annealingxe2x80x9d, DRC Conference Digest, 2002, pp. 49-50). A suitable post-recrystallization anneal for improving the film quality within silicon recrystallized by MILC is accomplished by exposing recrystallized material to a temperature of from about 850xc2x0 C. to about 900xc2x0 C. under an inert ambient (with a suitable ambient comprising, for example, N2). MILC can allow nearly single crystal silicon grains to be formed in predefined amorphous-silicon islands for device channel regions. Nickel-induced-lateral-recrystallization can allow device properties to approach those of single crystal silicon.
The carrier mobility of a transistor channel region can be significantly enhanced if the channel region is made of a semiconductor material having a strained crystalline lattice (such as, for example, a silicon/germanium material having a strained lattice, or a silicon material having a strained lattice) formed over a semiconductor material having a relaxed lattice (such as, for example, a silicon/germanium material having a relaxed crystalline lattice). (See, for example, Rim, K. et al., xe2x80x9cStrained Si NMOSFETs for High Performance CMOS Technologyxe2x80x9d, VLSI Tech. Digest, 2001, p. 5960; Cheng, Z. et al., xe2x80x9cSiGe-On-Insulator (SGOI) Substrate Preparation and MOSFET Fabrication for Electron Mobility Evaluationxe2x80x9d 2001 IEEE SOI Conference Digest, October 2001, pp. 13-14; Huang, L. J. et al., xe2x80x9cCarrier Mobility Enhancement in Strained Si-on-Insulator Fabricated by Wafer Bondingxe2x80x9d, VLSI Tech. Digest, 2001, pp. 57-58; and Mizuno, T. et al., xe2x80x9cHigh Performance CMOS Operation of Strained-SOI MOSFETs Using Thin Film SiGe-on-Insulator Substratexe2x80x9d, VLSI Tech. Digest, 2002, p. 106-107.)
The terms xe2x80x9crelaxed crystalline latticexe2x80x9d and xe2x80x9cstrained crystalline latticexe2x80x9d are utilized to refer to crystalline lattices which are within a defined lattice configuration for the semiconductor material, or perturbed from the defined lattice configuration, respectively. In applications in which the relaxed lattice material comprises silicon/germanium having a germanium concentration of from 10% to 60%, mobility enhancements of 110% for electrons and 60-80% for holes can be accomplished by utilizing a strained lattice material in combination with the relaxed lattice material (see for example, Rim, K. et al., xe2x80x9cCharacteristics and Device Design of Sub-100 nm Strained SiN and PMOSFETsxe2x80x9d, VLSI Tech. Digest, 2002, 00. 98-99; and Huang, L. J. et al., xe2x80x9cCarrier Mobility Enhancement in Strained Si-on-Insulator Fabricated by Wafer Bondingxe2x80x9d, VLSI Tech. Digest, 2001, pp. 57-58).
Performance enhancements of standard field effect transistor devices are becoming limited with progressive lithographic scaling in conventional applications. Accordingly, strained-lattice-channeled-field effect transistors on relaxed silicon/germanium offers an opportunity to enhance device performance beyond that achieved through conventional lithographic scaling. IBM recently announced the world""s fastest communications chip following the approach of utilizing a strained crystalline lattice over a relaxed crystalline lattice (see, for example, xe2x80x9cIBM Builds World""s Fastest Communications Microchipxe2x80x9d, Reuters U.S. Company News, Feb. 25, 2002; and Markoff, J., xe2x80x9cIBM Circuits are Now Faster and Reduce Use of Powerxe2x80x9d, The New York Times, Feb. 25, 2002).
Although various techniques have been developed for substantially controlling nucleation and grain growth processes of semiconductor materials, grain orientation control is lacking. Further, the post-anneal treatment utilized in conjunction with MILC can be unsuitable in applications in which a low thermal budget is desired. Among the advantages of the invention described below is that such can allow substantial control of crystal grain orientation within a semiconductor material, while lowering thermal budget requirements relative to conventional methods. Additionally, the quality of the grown crystal formed from a semiconductor material can be improved relative to that of conventional methods.
In further aspects of the prior art, non-volatile memory devices (such as, for example, EPROM devices, EEPROM devices, and flash devices) are commonly utilized for data and program storage, while non-volatile logic devices (such as FPGA devices) are used in logic elements.
It is common for non-volatile constructions to include an electrically floating element (such as a floating gate or plate), separated from a semiconductor substrate by a dielectric material (such as a tunnel oxide). A pair of source/drain regions extend into the semiconductor substrate, and are gatedly connected to one another through the floating element. A control gate is provided over the floating element, and is separated from the floating element by appropriate insulating material.
The floating element can store charge, and, depending on the amount of stored charge, assumes one of two or more stable states. The various stable states of the floating element can be assigned values, and thus can be utilized to retain information. For instance, one of the stable states can be assigned the value xe2x80x9c1xe2x80x9d and another of the stable states can be assigned the value xe2x80x9c0xe2x80x9d.
A continuing goal in semiconductor processing is to increase performance of devices while maintaining, or even reducing, a footprint associated with the devices. Accordingly, it is desirable to develop improved non-volatile devices.
The invention includes non-volatile devices associated with one or more Si/Ge materials. In particular aspects, the Si/Ge can be within a thin film contained within an SOI construction. For instance, the Si/Ge can be in the form of a crystalline layer having a thickness of less than or equal to about 2000 angstroms. The non-volatile device can include a media within which charge is stored (the media can be, for example, a floating gate or floating plate) over the crystalline Si/Ge, and a pair of source/drain regions proximate the media. The source/drain regions extend into the crystalline Si/Ge, and accordingly at least a portion of the source/drain regions are within the crystalline Si/Ge. A gate insulator is between the media and the crystalline Si/Ge. The portion of the source/drain regions within the crystalline material is preferably contained within a single crystal of the material. The memory device can further include an insulative material over the media, and a control gate separated from the media by the insulative material. In further aspects of the invention, the crystalline layer comprising Si/Ge can have a relaxed crystalline lattice, and a crystalline layer having a strained crystalline lattice can be formed between the layer having the relaxed crystalline lattice and the gate insulator.
In aspects of the invention in which the Si/Ge is associated with an SOI construction, a base (or substrate) of the construction can be selected from a vast number of materials, including, for example, semiconductive materials, glass, aluminum oxide, silicon dioxide, metal and plastic.
In further aspects, the invention encompasses electronic systems comprising novel non-volatile memory and/or logic devices.